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Message-ID: <CAJ2_jOG9Ag0spbh3YCxavUE5XEAUP1pHcgCZ56Nu2u4TqfrzHQ@mail.gmail.com>
Date:   Tue, 21 May 2019 11:00:59 +0530
From:   Yash Shah <yash.shah@...ive.com>
To:     linux-edac@...r.kernel.org, linux-riscv@...ts.infradead.org,
        Palmer Dabbelt <palmer@...ive.com>,
        Borislav Petkov <bp@...en8.de>,
        James Morse <james.morse@....com>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        linux-kernel@...r.kernel.org, aou@...s.berkeley.edu,
        mchehab@...nel.org, Sachin Ghadi <sachin.ghadi@...ive.com>,
        davem@...emloft.net, gregkh@...uxfoundation.org,
        nicolas.ferre@...rochip.com, paulmck@...ux.ibm.com
Subject: Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs

On Mon, May 6, 2019 at 4:57 PM Yash Shah <yash.shah@...ive.com> wrote:
>
> The initial ver of EDAC driver supports:
> - ECC event monitoring and reporting through the EDAC framework for SiFive
>   L2 cache controller.
>
> The EDAC driver registers for notifier events from the L2 cache controller
> driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events
>
> Signed-off-by: Yash Shah <yash.shah@...ive.com>
> Reviewed-by: James Morse <james.morse@....com>
> ---
> This patch depends on patch
> 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs'
> https://lkml.org/lkml/2019/5/6/255

The prerequisite patch (sifive_l2_cache driver) has been merged into
mainline v5.2-rc1
It should be OK to merge this edac driver now.

- Yash

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