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Date: Tue, 21 May 2019 16:51:36 +0200 From: Paul Cercueil <paul@...pouillou.net> To: Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Ralf Baechle <ralf@...ux-mips.org>, Paul Burton <paul.burton@...s.com>, James Hogan <jhogan@...nel.org>, Jonathan Corbet <corbet@....net>, Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Jason Cooper <jason@...edaemon.net>, Marc Zyngier <marc.zyngier@....com>, Lee Jones <lee.jones@...aro.org> Cc: Mathieu Malaterre <malat@...ian.org>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-mips@...r.kernel.org, linux-doc@...r.kernel.org, linux-clk@...r.kernel.org, od@...c.me, Paul Cercueil <paul@...pouillou.net>, Rob Herring <robh@...nel.org> Subject: [PATCH v12 08/13] clk: jz4740: Add TCU clock Add the missing TCU clock to the list of clocks supplied by the CGU for the JZ4740 SoC. Signed-off-by: Paul Cercueil <paul@...pouillou.net> Acked-by: Stephen Boyd <sboyd@...nel.org> Acked-by: Rob Herring <robh@...nel.org> --- Notes: v5: New patch v6-v12: No change drivers/clk/ingenic/jz4740-cgu.c | 6 ++++++ include/dt-bindings/clock/jz4740-cgu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 25f7df028e67..fbc7319c2861 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -212,6 +212,12 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 5 }, }, + + [JZ4740_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, }; static void __init jz4740_cgu_init(struct device_node *np) diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h index 6ed83f926ae7..e82d77028581 100644 --- a/include/dt-bindings/clock/jz4740-cgu.h +++ b/include/dt-bindings/clock/jz4740-cgu.h @@ -34,5 +34,6 @@ #define JZ4740_CLK_ADC 19 #define JZ4740_CLK_I2C 20 #define JZ4740_CLK_AIC 21 +#define JZ4740_CLK_TCU 22 #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ -- 2.21.0.593.g511ec345e18
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