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Message-Id: <20190521145141.9813-13-paul@crapouillou.net>
Date: Tue, 21 May 2019 16:51:40 +0200
From: Paul Cercueil <paul@...pouillou.net>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>,
Jonathan Corbet <corbet@....net>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
Lee Jones <lee.jones@...aro.org>
Cc: Mathieu Malaterre <malat@...ian.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-mips@...r.kernel.org,
linux-doc@...r.kernel.org, linux-clk@...r.kernel.org, od@...c.me,
Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH v12 12/13] MIPS: GCW0: Reduce system timer and clocksource to 750 kHz
The default clock (12 MHz) is too fast for the system timer.
Signed-off-by: Paul Cercueil <paul@...pouillou.net>
---
Notes:
v8: New patch
v9: Don't configure clock timer1, as the OS Timer is used as
clocksource on this SoC
v10: Revert back to v8 bahaviour. Let the user choose what
clocksource should be used.
v11: No change
v12: Move clocksource to channel 2, as channel 1 is used as PWM
for the backlight.
arch/mips/boot/dts/ingenic/gcw0.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
index 35f0291e8d38..f58d239c2058 100644
--- a/arch/mips/boot/dts/ingenic/gcw0.dts
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -2,6 +2,7 @@
/dts-v1/;
#include "jz4770.dtsi"
+#include <dt-bindings/clock/ingenic,tcu.h>
/ {
compatible = "gcw,zero", "ingenic,jz4770";
@@ -60,3 +61,12 @@
/* The WiFi module is connected to the UHC. */
status = "okay";
};
+
+&tcu {
+ /* 750 kHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+ assigned-clock-rates = <750000>, <750000>;
+
+ /* PWM1 is in use, so reserve channel #2 for the clocksource */
+ ingenic,pwm-channels-mask = <0xfa>;
+};
--
2.21.0.593.g511ec345e18
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