[<prev] [next>] [day] [month] [year] [list]
Message-ID: <20190522222756.10323-1-kim.phillips@amd.com>
Date: Wed, 22 May 2019 22:28:10 +0000
From: "Phillips, Kim" <kim.phillips@....com>
To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC: "Phillips, Kim" <kim.phillips@....com>,
"Natarajan, Janakarajan" <Janakarajan.Natarajan@....com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>, Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Borislav Petkov <bp@...e.de>,
Martin Liška <mliska@...e.cz>,
Thomas Richter <tmricht@...ux.ibm.com>,
Hendrik Brueckner <brueckner@...ux.ibm.com>
Subject: [PATCH] perf vendor events amd: add L3 cache events for Family 17h
From: Kim Phillips <kim.phillips@....com>
Allow users to symbolically specify L3 events for Family 17h processors
using the existing AMD Uncore driver.
Signed-off-by: Kim Phillips <kim.phillips@....com>
Cc: Janakarajan Natarajan <Janakarajan.Natarajan@....com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Andi Kleen <ak@...ux.intel.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Borislav Petkov <bp@...e.de>
Cc: "Martin Liška" <mliska@...e.cz>
Cc: Thomas Richter <tmricht@...ux.ibm.com>
Cc: Hendrik Brueckner <brueckner@...ux.ibm.com>
Cc: linux-kernel@...r.kernel.org
---
.../perf/pmu-events/arch/x86/amdfam17h/cache.json | 14 ++++++++++++++
tools/perf/pmu-events/jevents.c | 1 +
2 files changed, 15 insertions(+)
diff --git a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
index 5d9f9e172743..e38adf8927ae 100644
--- a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
+++ b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json
@@ -311,5 +311,19 @@
"BriefDescription": "Total cycles spent with one or more fill requests in flight from L2.",
"PublicDescription": "Total cycles spent with one or more fill requests in flight from L2.",
"UMask": "0x1"
+ },
+ {
+ "EventName": "l3_request_g1.caching_l3_cache_accesses",
+ "EventCode": "0x01",
+ "BriefDescription": "L3 cache accesses",
+ "UMask": "0x80",
+ "Unit": "L3PMC"
+ },
+ {
+ "EventName": "l3_comb_clstr_state.request_miss",
+ "EventCode": "0x06",
+ "BriefDescription": "L3 cache misses",
+ "UMask": "0x01",
+ "Unit": "L3PMC"
}
]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index 58f77fd0f59f..fb2cc98c5b0e 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -236,6 +236,7 @@ static struct map {
{ "CPU-M-CF", "cpum_cf" },
{ "CPU-M-SF", "cpum_sf" },
{ "UPI LL", "uncore_upi" },
+ { "L3PMC", "amd_l3" },
{}
};
--
2.21.0
Powered by blists - more mailing lists