linux-kernel - [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <PS2P216MB0642AD5BCA377FDC5DCD8A7B80000@PS2P216MB0642.KORP216.PROD.OUTLOOK.COM>
Date:   Wed, 22 May 2019 14:30:30 +0000
From:   Nicholas Johnson <nicholas.johnson-opensource@...look.com.au>
To:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>,
        "corbet@....net" <corbet@....net>,
        Nicholas Johnson <nicholas.johnson-opensource@...look.com.au>
Subject: [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any
 BIOS support

Rebase patches to apply cleanly to 5.2-rc1 source. Remove patch for 
comment style cleanup as this has already been applied.

Anybody interested in testing, you can do so with:

a) Intel system with Thunderbolt 3 and native enumeration. The Gigabyte 
Z390 Designare is one of the most perfect for this that I have never had 
the opportunity to use - it does not even have the option for BIOS 
assisted enumeration present in the BIOS.

b) Any system with PCIe and the Gigabyte GC-TITAN RIDGE add-in card, 
jump the header as described and use kernel parameters like:

pci=assign-busses,hpbussize=0x33,realloc,hpmemsize=128M,hpmemprefsize=1G,nocrs 
pcie_ports=native

[optional] pci.dyndbg

    ___
 __/   \__
|o o o o o| When looking into the receptacle on back of PCIe card.
|_________| Jump pins 3 and 5.

 1 2 3 4 5

The Intel system is nice in that it should just work. The add-in card 
setup is nice in that you can go nuts and assign copious amounts of 
MMIO_PREF - can anybody show a Xeon Phi coprocessor with 16G BAR working 
in an eGPU enclosure with these patches?

However, if you specify the above kernel parameters on the Intel system, 
you should be able to override it to allocate more space.

Nicholas Johnson (4):
  PCI: Consider alignment of hot-added bridges when distributing
    available resources
  PCI: Modify extend_bridge_window() to set resource size directly
  PCI: Fix bug resulting in double hpmemsize being assigned to MMIO
    window
  PCI: Add pci=hpmemprefsize parameter to set MMIO_PREF size
    independently

 .../admin-guide/kernel-parameters.txt         |   7 +-
 drivers/pci/pci.c                             |  18 +-
 drivers/pci/setup-bus.c                       | 265 ++++++++++--------
 include/linux/pci.h                           |   3 +-
 4 files changed, 167 insertions(+), 126 deletions(-)

-- 
2.20.1