linux-kernel - [PATCH 4.14 25/77] clk: hi3660: Mark clk_gate_ufs

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Date:   Thu, 23 May 2019 21:05:43 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Zhong Kaihua <zhongkaihua@...wei.com>,
        John Stultz <john.stultz@...aro.org>,
        Zhangfei Gao <zhangfei.gao@...aro.org>,
        Dong Zhang <zhangdong46@...ilicon.com>,
        Leo Yan <leo.yan@...aro.org>, Stephen Boyd <sboyd@...nel.org>
Subject: [PATCH 4.14 25/77] clk: hi3660: Mark clk_gate_ufs_subsys as critical

From: Leo Yan <leo.yan@...aro.org>

commit 9f77a60669d13ed4ddfa6cd7374c9d88da378ffa upstream.

clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow.  Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.

Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: stable@...r.kernel.org
Cc: Zhong Kaihua <zhongkaihua@...wei.com>
Cc: John Stultz <john.stultz@...aro.org>
Cc: Zhangfei Gao <zhangfei.gao@...aro.org>
Suggested-by: Dong Zhang <zhangdong46@...ilicon.com>
Signed-off-by: Leo Yan <leo.yan@...aro.org>
Signed-off-by: Stephen Boyd <sboyd@...nel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/clk/hisilicon/clk-hi3660.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -163,8 +163,12 @@ static const struct hisi_gate_clock hi36
 	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
 	{ HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
 	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
+	/*
+	 * clk_gate_ufs_subsys is a system bus clock, mark it as critical
+	 * clock and keep it on for system suspend and resume.
+	 */
 	{ HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
-	  CLK_SET_RATE_PARENT, 0x50, 21, 0, },
+	  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
 	{ HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
 	  CLK_SET_RATE_PARENT, 0x50, 28, 0, },
 	{ HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",