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Message-ID: <20190523225052.GA29562@Asurada-Nvidia.nvidia.com>
Date: Thu, 23 May 2019 15:50:52 -0700
From: Nicolin Chen <nicoleotsuka@...il.com>
To: "broonie@...nel.org" <broonie@...nel.org>,
"S.j. Wang" <shengjiu.wang@....com>
Cc: "timur@...nel.org" <timur@...nel.org>,
"Xiubo.Lee@...il.com" <Xiubo.Lee@...il.com>,
"festevam@...il.com" <festevam@...il.com>,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ASoC: fsl_esai: fix the channel swap issue after xrun
On Thu, May 23, 2019 at 11:04:03AM +0000, S.j. Wang wrote:
> > On Thu, May 23, 2019 at 09:53:42AM +0000, S.j. Wang wrote:
> > > > > + /*
> > > > > + * Add fifo reset here, because the regcache_sync will
> > > > > + * write one more data to ETDR.
> > > > > + * Which will cause channel shift.
> > > >
> > > > Sounds like a bug to me...should fix it first by marking the data
> > > > registers as volatile.
> > > >
> > > The ETDR is a writable register, it is not volatile. Even we change it
> > > to Volatile, I don't think we can't avoid this issue. for the
> > > regcache_sync Just to write this register, it is correct behavior.
> >
> > Is that so? Quoting the comments of regcache_sync():
> > "* regcache_sync - Sync the register cache with the hardware.
> > *
> > * @map: map to configure.
> > *
> > * Any registers that should not be synced should be marked as
> > * volatile."
> >
> > If regcache_sync() does sync volatile registers too as you said, I don't mind
> > having this FIFO reset WAR for now, though I think this mismatch between
> > the comments and the actual behavior then should get people's attention.
> >
> > Thank you
>
> ETDR is not volatile, if we mark it is volatile, is it correct?
Well, you have a point -- it might not be ideally true, but it sounds
like a correct fix to me according to this comments.
We can wait for Mark's comments or just send a patch to the mail list
for review.
Thanks you
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