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Message-Id: <1558636616-4891-2-git-send-email-kan.liang@linux.intel.com>
Date: Thu, 23 May 2019 11:36:56 -0700
From: kan.liang@...ux.intel.com
To: vincent.weaver@...ne.edu
Cc: ak@...ux.intel.com, peterz@...radead.org,
alexander.shishkin@...ux.intel.com, acme@...hat.com,
jolsa@...hat.com, eranian@...gle.com, mingo@...nel.org,
linux-kernel@...r.kernel.org, Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH 2/2] perf/x86/regs: Check reserved bits
From: Kan Liang <kan.liang@...ux.intel.com>
The perf fuzzer triggers a warning which map to:
if (WARN_ON_ONCE(idx >= ARRAY_SIZE(pt_regs_offset)))
return 0;
The bits between XMM registers and generic registers are reserved.
But perf_reg_validate() doesn't check these bits.
Add REG_RESERVED for reserved bits.
Check the reserved bits in perf_reg_validate().
Fixes: 878068ea270e ("perf/x86: Support outputting XMM registers")
Reported-by: Vince Weaver <vincent.weaver@...ne.edu>
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/kernel/perf_regs.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 86ffe5a..3f8c1fc 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -79,6 +79,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
return regs_get_register(regs, pt_regs_offset[idx]);
}
+#define REG_RESERVED (((1ULL << PERF_REG_X86_XMM0) - 1) & \
+ ~((1ULL << PERF_REG_X86_MAX) - 1))
+
#ifdef CONFIG_X86_32
#define REG_NOSUPPORT ((1ULL << PERF_REG_X86_R8) | \
(1ULL << PERF_REG_X86_R9) | \
@@ -91,7 +94,7 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
int perf_reg_validate(u64 mask)
{
- if (!mask || (mask & REG_NOSUPPORT))
+ if (!mask || (mask & (REG_NOSUPPORT | REG_RESERVED)))
return -EINVAL;
return 0;
@@ -117,7 +120,7 @@ void perf_get_regs_user(struct perf_regs *regs_user,
int perf_reg_validate(u64 mask)
{
- if (!mask || (mask & REG_NOSUPPORT))
+ if (!mask || (mask & (REG_NOSUPPORT | REG_RESERVED)))
return -EINVAL;
return 0;
--
2.7.4
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