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Message-Id: <20190525.110252.292904127953775877.davem@davemloft.net>
Date: Sat, 25 May 2019 11:02:52 -0700 (PDT)
From: David Miller <davem@...emloft.net>
To: biao.huang@...iatek.com
Cc: joabreu@...opsys.com, peppe.cavallaro@...com,
alexandre.torgue@...com, mcoquelin.stm32@...il.com,
matthias.bgg@...il.com, netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org, yt.shen@...iatek.com,
jianguo.zhang@...iatek.comi, boon.leong.ong@...el.com
Subject: Re: [v4, PATCH 0/3] fix some bugs in stmmac
From: Biao Huang <biao.huang@...iatek.com>
Date: Fri, 24 May 2019 14:26:06 +0800
> changes in v4:
> since MTL_OPERATION_MODE write back issue has be fixed in the latest driver,
> remove original patch#3
>
> changes in v3:
> add a Fixes:tag for each patch
>
> changes in v2:
> 1. update rx_tail_addr as Jose's comment
> 2. changes clk_csr condition as Alex's proposition
> 3. remove init lines in dwmac-mediatek, get clk_csr from dts instead.
>
> v1:
> This series fix some bugs in stmmac driver
> 3 patches are for common stmmac or dwmac4:
> 1. update rx tail pointer to fix rx dma hang issue.
> 2. change condition for mdc clock to fix csr_clk can't be zero issue.
> 3. write the modified value back to MTL_OPERATION_MODE.
> 1 patch is for dwmac-mediatek:
> modify csr_clk value to fix mdio read/write fail issue for dwmac-mediatek
Series applied, thanks.
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