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Message-ID: <20190527060656.GA7997@kroah.com>
Date: Mon, 27 May 2019 08:06:56 +0200
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: Shaokun Zhang <zhangshaokun@...ilicon.com>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
"Rafael J. Wysocki" <rafael@...nel.org>,
Sudeep Holla <sudeep.holla@....com>,
Catalin Marinas <catalin.marinas@....com>,
Jeremy Linton <jeremy.linton@....com>,
Will Deacon <will.deacon@....com>
Subject: Re: [PATCH v3 1/2] drivers: base: cacheinfo: Add variable to record
max cache line size
On Mon, May 27, 2019 at 10:06:07AM +0800, Shaokun Zhang wrote:
> Add coherency_max_size variable to record the maximum cache line size
> for different cache levels. We will synchronize it with CTR_EL0.CWG
> reporting in cache_line_size() for arm64.
>
> Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> Cc: "Rafael J. Wysocki" <rafael@...nel.org>
> Cc: Sudeep Holla <sudeep.holla@....com>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Jeremy Linton <jeremy.linton@....com>
> Cc: Will Deacon <will.deacon@....com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@...ilicon.com>
> ---
> ChangeLog since v2:
> -- Rebase to 5.2-rc2
> -- Export cache_line_size for I/O driver
> ChangeLog since v1:
> -- Move coherency_max_size to drivers/base/cacheinfo.c
> -- Address Catalin's comments
> Link: https://www.spinics.net/lists/arm-kernel/msg723615.html
>
> drivers/base/cacheinfo.c | 5 +++++
> include/linux/cacheinfo.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index a7359535caf5..8827c60f51e2 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -213,6 +213,8 @@ int __weak cache_setup_acpi(unsigned int cpu)
> return -ENOTSUPP;
> }
>
> +unsigned int coherency_max_size;
Why are you creating a global variable?
Where are the other patches in this series?
thanks,
greg k-h
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