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Message-ID: <20190528100147.GM2623@hirez.programming.kicks-ass.net>
Date: Tue, 28 May 2019 12:01:47 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Jiri Olsa <jolsa@...nel.org>
Cc: "Liang, Kan" <kan.liang@...ux.intel.com>,
Stephane Eranian <eranian@...gle.com>,
Andy Lutomirski <luto@...nel.org>,
lkml <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>,
Vince Weaver <vincent.weaver@...ne.edu>,
Thomas Gleixner <tglx@...utronix.de>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: [PATCH 0/8] perf/x86: Rework msr probe interface
On Mon, May 27, 2019 at 11:51:21PM +0200, Jiri Olsa wrote:
> hi,
> following up on [1], [2] and [3], this patchset adds update
> attribute groups to pmu, factors out the MSR probe code and
> use it in msr,cstate* and rapl PMUs.
>
> The functionality stays the same with one exception:
> the event is not exported if the rdmsr return zero
> on event's msr.
That seems a wee bit dangerous, are we sure none of these counters are 0
by 'accident' when we probe them? I'm thinking esp. things like the Cn
residency stuff could be 0 simply because we've not been into that state
yet.
Other than that, this looks good. Kan?
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