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Message-ID: <20190528181159.GA24853@roeck-us.net>
Date: Tue, 28 May 2019 11:11:59 -0700
From: Guenter Roeck <linux@...ck-us.net>
To: Paul Cercueil <paul@...pouillou.net>
Cc: Wim Van Sebroeck <wim@...ux-watchdog.org>, od@...c.me,
linux-watchdog@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] watchdog: jz4740: Use register names from
<linux/mfd/ingenic-tcu.h>
On Tue, May 21, 2019 at 05:53:10PM +0200, Paul Cercueil wrote:
> Use the macros from <linux/mfd/ingenic-tcu.h> instead of declaring our
> own.
>
> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
Reviewed-by: Guenter Roeck <linux@...ck-us.net>
> ---
> drivers/watchdog/jz4740_wdt.c | 39 ++++++++++++++---------------------
> 1 file changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
> index d1bc7cbd4f2b..51be321c775a 100644
> --- a/drivers/watchdog/jz4740_wdt.c
> +++ b/drivers/watchdog/jz4740_wdt.c
> @@ -13,6 +13,7 @@
> *
> */
>
> +#include <linux/mfd/ingenic-tcu.h>
> #include <linux/module.h>
> #include <linux/moduleparam.h>
> #include <linux/types.h>
> @@ -28,23 +29,16 @@
>
> #include <asm/mach-jz4740/timer.h>
>
> -#define JZ_REG_WDT_TIMER_DATA 0x0
> -#define JZ_REG_WDT_COUNTER_ENABLE 0x4
> -#define JZ_REG_WDT_TIMER_COUNTER 0x8
> -#define JZ_REG_WDT_TIMER_CONTROL 0xC
> -
> #define JZ_WDT_CLOCK_PCLK 0x1
> #define JZ_WDT_CLOCK_RTC 0x2
> #define JZ_WDT_CLOCK_EXT 0x4
>
> -#define JZ_WDT_CLOCK_DIV_SHIFT 3
> -
> -#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
> -#define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
> -#define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
> -#define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
> -#define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
> -#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
> +#define JZ_WDT_CLOCK_DIV_1 (0 << TCU_TCSR_PRESCALE_LSB)
> +#define JZ_WDT_CLOCK_DIV_4 (1 << TCU_TCSR_PRESCALE_LSB)
> +#define JZ_WDT_CLOCK_DIV_16 (2 << TCU_TCSR_PRESCALE_LSB)
> +#define JZ_WDT_CLOCK_DIV_64 (3 << TCU_TCSR_PRESCALE_LSB)
> +#define JZ_WDT_CLOCK_DIV_256 (4 << TCU_TCSR_PRESCALE_LSB)
> +#define JZ_WDT_CLOCK_DIV_1024 (5 << TCU_TCSR_PRESCALE_LSB)
>
> #define DEFAULT_HEARTBEAT 5
> #define MAX_HEARTBEAT 2048
> @@ -72,7 +66,7 @@ static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
> {
> struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
>
> - writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
> + writew(0x0, drvdata->base + TCU_REG_WDT_TCNT);
> return 0;
> }
>
> @@ -95,18 +89,17 @@ static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
> break;
> }
> timeout_value >>= 2;
> - clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
> + clock_div += (1 << TCU_TCSR_PRESCALE_LSB);
> }
>
> - writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
> - writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
> + writeb(0x0, drvdata->base + TCU_REG_WDT_TCER);
> + writew(clock_div, drvdata->base + TCU_REG_WDT_TCSR);
>
> - writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
> - writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
> - writew(clock_div | JZ_WDT_CLOCK_RTC,
> - drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
> + writew((u16)timeout_value, drvdata->base + TCU_REG_WDT_TDR);
> + writew(0x0, drvdata->base + TCU_REG_WDT_TCNT);
> + writew(clock_div | JZ_WDT_CLOCK_RTC, drvdata->base + TCU_REG_WDT_TCSR);
>
> - writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
> + writeb(0x1, drvdata->base + TCU_REG_WDT_TCER);
>
> wdt_dev->timeout = new_timeout;
> return 0;
> @@ -124,7 +117,7 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
> {
> struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
>
> - writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
> + writeb(0x0, drvdata->base + TCU_REG_WDT_TCER);
> jz4740_timer_disable_watchdog();
>
> return 0;
> --
> 2.21.0.593.g511ec345e18
>
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