linux-kernel - Re: [PATCH 2/3] ARM: dts: imx6: rdu2: Disable WP for USDHC2 and USDHC3

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 29 May 2019 10:27:29 +0200
From:   Lucas Stach <l.stach@...gutronix.de>
To:     Andrey Smirnov <andrew.smirnov@...il.com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     Chris Healy <cphealy@...il.com>, Shawn Guo <shawnguo@...nel.org>,
        Fabio Estevam <festevam@...il.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] ARM: dts: imx6: rdu2: Disable WP for USDHC2 and
 USDHC3

Am Mittwoch, den 29.05.2019, 00:18 -0700 schrieb Andrey Smirnov:
> RDU2 production units come with resistor connecting WP pin to
> correpsonding GPIO DNPed for both SD card slots. Drop any WP related
> configuration and mark both slots with "disable-wp".
> 
> > Reported-by: Chris Healy <cphealy@...il.com>
> > Reviewed-by: Chris Healy <cphealy@...il.com>
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
> > Cc: Shawn Guo <shawnguo@...nel.org>
> > Cc: Fabio Estevam <festevam@...il.com>
> > Cc: Lucas Stach <l.stach@...gutronix.de>
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org

Reviewed-by: Lucas Stach <l.stach@...gutronix.de>

> ---
>  arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> index 07e21d1e5b4c..04d4d4d7e43c 100644
> --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
> @@ -658,7 +658,7 @@
> >  	pinctrl-0 = <&pinctrl_usdhc2>;
> >  	bus-width = <4>;
> >  	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
> > -	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> > +	disable-wp;
> >  	vmmc-supply = <&reg_3p3v_sd>;
> >  	vqmmc-supply = <&reg_3p3v>;
> >  	no-1-8-v;
> @@ -671,7 +671,7 @@
> >  	pinctrl-0 = <&pinctrl_usdhc3>;
> >  	bus-width = <4>;
> >  	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
> > -	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
> > +	disable-wp;
> >  	vmmc-supply = <&reg_3p3v_sd>;
> >  	vqmmc-supply = <&reg_3p3v>;
> >  	no-1-8-v;
> @@ -1096,7 +1096,6 @@
> > >  			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
> > >  			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
> > >  			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
> > > -			MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x40010040
> > >  			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x40010040
> >  		>;
> >  	};
> @@ -1109,7 +1108,6 @@
> > >  			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
> > >  			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
> > >  			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
> > > -			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x40010040
> > >  			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x40010040
>  
> >  		>;