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Message-Id: <20190529083254.39581-3-chuanhua.han@nxp.com>
Date: Wed, 29 May 2019 16:32:54 +0800
From: Chuanhua Han <chuanhua.han@....com>
To: shawnguo@...nel.org, leoyang.li@....com, robh+dt@...nel.org,
mark.rutland@....com, linus.walleij@...aro.org,
bgolaszewski@...libre.com
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Chuanhua Han <chuanhua.han@....com>
Subject: [PATCH 3/3] arm64: dts: ls1088a: Revise gpio registers to little-endian
Since fsl-ls1088a Soc GPIO registers are used as little endian,
the patch adds the little-endian attribute to each gpio node.
Signed-off-by: Chuanhua Han <chuanhua.han@....com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137ffa319..3e6d20d065bd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -272,6 +272,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -282,6 +283,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -292,6 +294,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -302,6 +305,7 @@
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.17.1
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