linux-kernel - Re: [PATCH] x86/power: Fix 'nosmt' vs. hibernation triple fault during resume

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Date:   Wed, 29 May 2019 11:03:30 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Jiri Kosina <jikos@...nel.org>
Cc:     "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Pavel Machek <pavel@....cz>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Josh Poimboeuf <jpoimboe@...hat.com>, x86@...nel.org,
        linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86/power: Fix 'nosmt' vs. hibernation triple fault
 during resume

On Tue, May 28, 2019 at 11:31:45PM +0200, Jiri Kosina wrote:

> diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
> index a7d966964c6f..bde8ce1f6c6c 100644
> --- a/arch/x86/power/cpu.c
> +++ b/arch/x86/power/cpu.c
> @@ -299,9 +299,20 @@ int hibernate_resume_nonboot_cpu_disable(void)
>  	 * address in its instruction pointer may not be possible to resolve
>  	 * any more at that point (the page tables used by it previously may
>  	 * have been overwritten by hibernate image data).
> +	 *
> +	 * First, make sure that we wake up all the potentially disabled SMT
> +	 * threads which have been initially brought up and then put into
> +	 * mwait/cpuidle sleep.
> +	 * Those will be put to proper (not interfering with hibernation
> +	 * resume) sleep afterwards, and the resumed kernel will decide itself
> +	 * what to do with them.
>  	 */
>  	smp_ops.play_dead = resume_play_dead;

Oooh, teh yuck!, but this explains my confusion from the other thread.

> +	ret = cpuhp_smt_enable();
> +	if (ret)
> +		goto out;
>  	ret = disable_nonboot_cpus();
> +out:
>  	smp_ops.play_dead = play_dead;
>  	return ret;
>  }

I think you can avoid the goto like:

	ret = cpuhp_smt_enable();
	if (ret)
		return ret;

	smp_ops.play_dead = resume_play_dead;
	ret = disable_nonboot_cpus();
	smp_ops.play_dead = play_dead;
	return ret;

We don't need the play dead change to online CPUs.