lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 29 May 2019 11:46:50 +0100
From:   Raphael Gault <raphael.gault@....com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        mingo@...hat.com, catalin.marinas@....com, will.deacon@....com,
        acme@...nel.org, mark.rutland@....com
Subject: Re: [RFC 4/7] arm64: pmu: Add function implementation to update event
 index in userpage.

Hi Peter,

On 5/29/19 10:46 AM, Peter Zijlstra wrote:
> On Tue, May 28, 2019 at 04:03:17PM +0100, Raphael Gault wrote:
>> +static int armv8pmu_access_event_idx(struct perf_event *event)
>> +{
>> +	if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
>> +		return 0;
>> +
>> +	/*
>> +	 * We remap the cycle counter index to 32 to
>> +	 * match the offset applied to the rest of
>> +	 * the counter indeces.
>> +	 */
>> +	if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
>> +		return 32;
>> +
>> +	return event->hw.idx;
> 
> Is there a guarantee event->hw.idx is never 0? Or should you, just like
> x86, use +1 here?
> 

You are right, I should use +1 here. Thanks for pointing that out.

>> +}

Thanks,

-- 
Raphael Gault

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ