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Message-ID: <20190529140533.GC17679@ulmo>
Date: Wed, 29 May 2019 16:05:33 +0200
From: Thierry Reding <thierry.reding@...il.com>
To: Sowjanya Komatineni <skomatineni@...dia.com>
Cc: jonathanh@...dia.com, tglx@...utronix.de, jason@...edaemon.net,
marc.zyngier@....com, linus.walleij@...aro.org, stefan@...er.ch,
mark.rutland@....com, pdeschrijver@...dia.com, pgaikwad@...dia.com,
sboyd@...nel.org, linux-clk@...r.kernel.org,
linux-gpio@...r.kernel.org, jckuo@...dia.com, josephl@...dia.com,
talho@...dia.com, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org, mperttunen@...dia.com,
spatra@...dia.com, robh+dt@...nel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH V2 12/12] soc/tegra: pmc: configure tegra deep sleep
control settings
On Tue, May 28, 2019 at 04:08:56PM -0700, Sowjanya Komatineni wrote:
> Tegra210 and prior Tegra chips have power request signal polarity,
> deep sleep entry and wake related timings which are platform specific
> that should be configured before entering into deep sleep.
>
> Below are the timings specific configurations for deep sleep and wake.
> - Core rail power-on stabilization timer
> - OSC clock stabilization timer after SOC rail power is stabilized.
> - Core power off time is the minimum wake delay to keep the system
> in deep sleep state irrespective of any quick wake event.
>
> These values depends on the discharge time of regulators and turn OFF
> time of the PMIC to allow the complete system to finish entering into
> deep sleep state.
>
> These values vary based on the platform design and are specified
> through the device tree.
>
> This patch has implementation to configure these configurations which
> are must to have for deep sleep state.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++
> drivers/soc/tegra/pmc.c | 18 ++++++++++++++++++
> 2 files changed, 25 insertions(+)
Please split up the DT and driver changes into separate patches.
Thierry
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