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Message-ID: <67a14915b99ee5d933ef9e7e056fc6e1935e775e.1559198255.git.nickhu@andestech.com>
Date: Thu, 30 May 2019 14:49:10 +0800
From: Nick Hu <nickhu@...estech.com>
To: <greentime@...estech.com>, <palmer@...ive.com>,
<albert@...ive.com>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <hch@...radead.org>
CC: Nick Hu <nickhu@...estech.com>, <green.hu@...il.com>
Subject: [PATCH v2] riscv: Fix udelay in RV32.
In RV32, udelay would delay the wrong cycle. When it shifts right
"UDELAY_SHITFT" bits, it either delays 0 cycle or 1 cycle. It only works
correctly in RV64. Because the 'ucycles' always needs to be 64 bits
variable.
Signed-off-by: Nick Hu <nickhu@...estech.com>
---
arch/riscv/lib/delay.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/lib/delay.c b/arch/riscv/lib/delay.c
index dce8ae24c6d3..ee6853c1e341 100644
--- a/arch/riscv/lib/delay.c
+++ b/arch/riscv/lib/delay.c
@@ -88,7 +88,7 @@ EXPORT_SYMBOL(__delay);
void udelay(unsigned long usecs)
{
- unsigned long ucycles = usecs * lpj_fine * UDELAY_MULT;
+ u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT;
if (unlikely(usecs > MAX_UDELAY_US)) {
__delay((u64)usecs * riscv_timebase / 1000000ULL);
--
2.17.0
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