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Date:   Thu, 30 May 2019 02:17:50 +0000
From:   Ran Wang <>
To:     Felipe Balbi <>
CC:     Greg Kroah-Hartman <>,
        "open list:DESIGNWARE USB3 DRD IP DRIVER" <>,
        open list <>,
        Rob Herring <>,
        "" <>
Subject: RE: [PATCH] usb: dwc3: Enable the USB snooping

Hi Felipe,

On Wednesday, May 29, 2019 18:25, Felipe Balbi wrote:
> Hi,
> Ran Wang <> writes:
> >> >> >> c) WHAT does this mean for PCI devices?
> >
> > According to DWC3 data book, I think this (PCI) mean to the case of 'master
> bus type = Native'
> > The data book describes this feature as 'system bus DMA option for the
> > master bus, which may be configured as AHB, AXI, or Native.' On Table
> > 6-5, it says when MBUS_TYPE is Native, the definition of 4 transfer types
> control bits [3-0] is 'Same as AXI'.
> >
> > However, as to the code implementation to be generic to both PCI and
> > AXI, I admit I don't have a perfect solution so far, only 2 proposals with
> concerns:
> >
> > a. Create another module driver like dwc3-exynos.c
> (arch/arm/boot/dts/wxynos54xx.dtsi)
> >     to contain above programming code. However, it will touch the same reg
> range of DWC3
> >     I think this is not good.
> I'd prefer avoiding another glue :-)

Got it.
> > b. Add #ifdef CONFIG_ARCH_LAYERSCAPE in drivers/usb/dwc3/core.c to
> constrain hacking code
> >    can only take effect for Layerscape (AXI case). I know it look ugly.
> >
> > Do you have any better advice on this (besides changed power on default
> value from HW perspective)?
> Maybe we don't need to care, actually. Since this property will only be needed
> for RTL instantiation that didn't configure these defaults properly during
> coreConsultant.

Ok, I think I could add information in bindings to highlight this setting might
be RTL instantiation (SoC) relevant to prevent misusing.

> >> >> >> Another question is: Why wasn't this setup properly during
> >> >> >> coreConsultant instantiation of the RTL? Do you have devices on
> >> >> >> the market already that need this or is this some early FPGA
> >> >> >> model or test-only
> >> >> ASIC?
> >
> > Several Layerscape platforms like LS1043ARDB, LS1046ARDB, etc. are
> > already on the market and have this issue. So I have to work out a SW patch to
> fix them.
> Thank you, now I'm certain that this is not some temporary solution :-)
> Thanks for going through this again. Please refresh the patch so we can try to
> get it merged.

Sure, as I know all LS1043A and LS1046A relevant platforms have added 'dma-coherent'
to DTS node of 'soc' in mainline, which means without this fix USB function will down
definitely, I will go through all update requirement we've discussed and work out
next version patch. Thank you.


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