lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 29 May 2019 20:04:11 -0700 From: Greg Kroah-Hartman <gregkh@...uxfoundation.org> To: linux-kernel@...r.kernel.org Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, stable@...r.kernel.org, Kan Liang <kan.liang@...ux.intel.com>, "Peter Zijlstra (Intel)" <peterz@...radead.org>, Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Arnaldo Carvalho de Melo <acme@...hat.com>, Jiri Olsa <jolsa@...hat.com>, Linus Torvalds <torvalds@...ux-foundation.org>, Stephane Eranian <eranian@...gle.com>, Thomas Gleixner <tglx@...utronix.de>, Vince Weaver <vincent.weaver@...ne.edu>, acme@...nel.org, jolsa@...nel.org, Ingo Molnar <mingo@...nel.org>, Sasha Levin <sashal@...nel.org> Subject: [PATCH 5.0 178/346] perf/x86/intel/cstate: Add Icelake support [ Upstream commit f08c47d1f86c6dc666c7e659d94bf6d4492aa9d7 ] Icelake uses the same C-state residency events as Sandy Bridge. Signed-off-by: Kan Liang <kan.liang@...ux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org> Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@...hat.com> Cc: Jiri Olsa <jolsa@...hat.com> Cc: Linus Torvalds <torvalds@...ux-foundation.org> Cc: Peter Zijlstra <peterz@...radead.org> Cc: Stephane Eranian <eranian@...gle.com> Cc: Thomas Gleixner <tglx@...utronix.de> Cc: Vince Weaver <vincent.weaver@...ne.edu> Cc: acme@...nel.org Cc: jolsa@...nel.org Link: https://lkml.kernel.org/r/20190402194509.2832-10-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@...nel.org> Signed-off-by: Sasha Levin <sashal@...nel.org> --- arch/x86/events/intel/cstate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 56194c571299f..4a650eb3d94a3 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -584,6 +584,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_X, glm_cstates), X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates), + + X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_MOBILE, snb_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); -- 2.20.1
Powered by blists - more mailing lists