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Message-ID: <20190531234501.32826-2-Yazen.Ghannam@amd.com>
Date: Fri, 31 May 2019 23:45:11 +0000
From: "Ghannam, Yazen" <Yazen.Ghannam@....com>
To: "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>
CC: "Ghannam, Yazen" <Yazen.Ghannam@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"bp@...en8.de" <bp@...en8.de>
Subject: [PATCH 1/8] EDAC/amd64: Fix number of DIMMs and Chip Select
bases/masks on Family17h
From: Yazen Ghannam <yazen.ghannam@....com>
...because AMD Family 17h systems support 2 DIMMs, 4 CS bases, and 2 CS
masks per channel.
Fixes: 07ed82ef93d6 ("EDAC, amd64: Add Fam17h debug output")
Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
---
drivers/edac/amd64_edac.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 873437be86d9..9fa2f205f05c 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -810,7 +810,7 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
- for (dimm = 0; dimm < 4; dimm++) {
+ for (dimm = 0; dimm < 2; dimm++) {
size0 = 0;
cs0 = dimm * 2;
@@ -942,6 +942,9 @@ static void prep_chip_selects(struct amd64_pvt *pvt)
} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
+ } else if (pvt->fam >= 0x17) {
+ pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
+ pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
} else {
pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
--
2.17.1
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