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Message-ID: <4ba6aac7-1286-3307-dc5f-ebb42468a604@linux.intel.com>
Date:   Mon, 3 Jun 2019 13:19:12 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     tglx@...utronix.de, mingo@...hat.com, linux-kernel@...r.kernel.org,
        acme@...nel.org, eranian@...gle.com, ak@...ux.intel.com
Subject: Re: [RESEND PATCH 0/6] Perf uncore support for Snow Ridge server



On 6/3/2019 12:34 PM, Peter Zijlstra wrote:
> On Tue, Apr 30, 2019 at 05:53:42PM -0700, kan.liang@...ux.intel.com wrote:
>> From: Kan Liang <kan.liang@...ux.intel.com>
>>
>> The patch series intends to enable perf uncore support for Snow Ridge
>> server.
>>
>> Here is the link for the uncore document.
>> https://cdrdv2.intel.com/v1/dl/getContent/611319
>>
>> Patch 1: Fixes a generic issue for uncore free-running counter, which
>> also impacts the Snow Ridge server.
>>
>> Patch 2-6: Perf uncore support for Snow Ridge server.
>>
>> Kan Liang (6):
>>    perf/x86/intel/uncore: Handle invalid event coding for free-running
>>      counter
>>    perf/x86/intel/uncore: Add uncore support for Snow Ridge server
>>    perf/x86/intel/uncore: Extract codes of box ref/unref
>>    perf/x86/intel/uncore: Support MMIO type uncore blocks
>>    perf/x86/intel/uncore: Clean up client IMC
>>    perf/x86/intel/uncore: Add IMC uncore support for Snow Ridge
>>
>>   arch/x86/events/intel/uncore.c       | 122 +++++--
>>   arch/x86/events/intel/uncore.h       |  41 ++-
>>   arch/x86/events/intel/uncore_snb.c   |  16 +-
>>   arch/x86/events/intel/uncore_snbep.c | 601 +++++++++++++++++++++++++++++++++++
>>   4 files changed, 737 insertions(+), 43 deletions(-)
> 
> Kan, we had horrible conflicts between this set and the topology
> s/pkg/die/ thing. I've attempted a rebase here:
> 
>    https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git/log/?h=perf/core
> 
> can you please double check?

There are two errors. I think they have been reported by 0-day.
Rest of the patches looks good.

The first one is from ("perf/x86/intel/uncore: Support MMIO type uncore 
blocks"). The fix is as below.

diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index baee051..8453e60 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1201,7 +1201,7 @@ static int uncore_event_cpu_offline(unsigned int cpu)
  	/* Clear the references */
  	die = topology_logical_die_id(cpu);
  	uncore_box_unref(uncore_msr_uncores, die);
-	uncore_box_unref(uncore_mmio_uncores, pkg);
+	uncore_box_unref(uncore_mmio_uncores, die);
  	return 0;
  }


The other is from ("perf/x86/intel/uncore: Add IMC uncore support for 
Snow Ridge"). The fix is as below.

diff --git a/arch/x86/events/intel/uncore_snbep.c 
b/arch/x86/events/intel/uncore_snbep.c
index f4e04d8..b10a5ec 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -4406,7 +4406,7 @@ static struct pci_dev *snr_uncore_get_mc_dev(int id)

  static void snr_uncore_mmio_init_box(struct intel_uncore_box *box)
  {
-	struct pci_dev *pdev = snr_uncore_get_mc_dev(box->pkgid);
+	struct pci_dev *pdev = snr_uncore_get_mc_dev(box->dieid);
  	unsigned int box_ctl = uncore_mmio_box_ctl(box);
  	resource_size_t addr;
  	u32 pci_dword;




Thanks,
Kan

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