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Message-Id: <20190603015020.41410-1-Anson.Huang@nxp.com>
Date: Mon, 3 Jun 2019 09:50:20 +0800
From: Anson.Huang@....com
To: robh+dt@...nel.org, mark.rutland@....com, shawnguo@...nel.org,
s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com,
leonard.crestez@....com, aisheng.dong@....com,
viresh.kumar@...aro.org, ping.bai@....com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Linux-imx@....com
Subject: [PATCH] arm64: dts: imx8mm: Move gic node into soc node
From: Anson Huang <Anson.Huang@....com>
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang <Anson.Huang@....com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index dc99f45..429312e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -169,15 +169,6 @@
clock-output-names = "clk_ext4";
};
- gic: interrupt-controller@...00000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
- <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -739,6 +730,15 @@
dma-names = "rx-tx";
status = "disabled";
};
+
+ gic: interrupt-controller@...00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x38800000 0x10000>, /* GIC Dist */
+ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
usbphynop1: usbphynop1 {
--
2.7.4
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