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Message-Id: <20190603142214.24686-1-helen.koike@collabora.com>
Date: Mon, 3 Jun 2019 11:22:15 -0300
From: Helen Koike <helen.koike@...labora.com>
To: linux-rockchip@...ts.infradead.org
Cc: kernel@...labora.com, ezequiel@...labora.com,
laurent.pinchart@...asonboard.com,
manivannan.sadhasivam@...aro.org,
Helen Koike <helen.koike@...labora.com>,
linux-arm-kernel@...ts.infradead.org,
Vicente Bergas <vicencb@...il.com>,
Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org,
Klaus Goger <klaus.goger@...obroma-systems.com>,
linux-kernel@...r.kernel.org,
Christoph Muellner <christoph.muellner@...obroma-systems.com>,
Randy Li <ayaka@...lik.info>,
Philipp Tomsich <philipp.tomsich@...obroma-systems.com>,
Rob Herring <robh+dt@...nel.org>,
Tony Xie <tony.xie@...k-chips.com>,
Mark Rutland <mark.rutland@....com>,
Viresh Kumar <viresh.kumar@...aro.org>,
Marc Zyngier <marc.zyngier@....com>,
Matthias Brugger <matthias.bgg@...il.com>
Subject: [PATCH] arm64: dts: rockchip: fix isp iommu clocks and power domain
isp iommu requires wrapper variants of the clocks.
noc variants are always on and using the wrapper variants will activate
{A,H}CLK_ISP{0,1} due to the hierarchy.
Also add the respective power domain.
Refer:
RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram
RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition
Signed-off-by: Helen Koike <helen.koike@...labora.com>
---
Hello,
I tested this using the isp patch set (which is not upstream
yet). Without this patch, streaming from the isp stalls.
I'm also enabling the power domain and removing the disable status,
please let me know if this should be done in a separated patch.
Thanks
Helen
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 196ac9b78076..89594a7276f4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1706,11 +1706,11 @@
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
- clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+ clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3399_PD_ISP0>;
rockchip,disable-mmu-reset;
- status = "disabled";
};
isp1_mmu: iommu@...24000 {
@@ -1718,11 +1718,11 @@
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
- clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+ clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3399_PD_ISP1>;
rockchip,disable-mmu-reset;
- status = "disabled";
};
hdmi_sound: hdmi-sound {
--
2.20.1
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