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Message-ID: <20190605173441.GA9903@e107155-lin>
Date: Wed, 5 Jun 2019 18:34:42 +0100
From: Sudeep Holla <sudeep.holla@....com>
To: Sricharan R <sricharan@...eaurora.org>
Cc: robh+dt@...nel.org, sboyd@...nel.org, linus.walleij@...aro.org,
agross@...nel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-soc@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Sudeep Holla <sudeep.holla@....com>
Subject: Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support
On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
> Add initial device tree support for the Qualcomm IPQ6018 SoC and
> CP01 evaluation board.
>
> Signed-off-by: Sricharan R <sricharan@...eaurora.org>
> Signed-off-by: Abhishek Sahu <absahu@...eaurora.org>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++
> 3 files changed, 267 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi
>
[...]
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x3>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
> + };
> +
> + pmuv8: pmu {
> + compatible = "arm,armv8-pmuv3";
We know these are Cortex-A53s, why not update these accordingly ?
--
Regards,
Sudeep
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