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Date:   Thu, 06 Jun 2019 16:00:49 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Jeffrey Hugo <jeffrey.l.hugo@...il.com>, mturquette@...libre.com
Cc:     agross@...nel.org, david.brown@...aro.org,
        bjorn.andersson@...aro.org, robh+dt@...nel.org,
        mark.rutland@....com, marc.w.gonzalez@...e.fr,
        jcrouse@...eaurora.org, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Jeffrey Hugo <jeffrey.l.hugo@...il.com>
Subject: Re: [PATCH 2/3] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver

Quoting Jeffrey Hugo (2019-05-28 09:48:03)
> diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
> new file mode 100644
> index 000000000000..e45062e40718
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-msm8998.c
> +
> +static int gpucc_msm8998_probe(struct platform_device *pdev)
> +{
> +       struct regmap *regmap;
> +       struct clk *xo;
> +
> +       /*
> +        * We must have a valid XO to continue until orphan probe defer is
> +        * implemented.
> +        */
> +       xo = clk_get(&pdev->dev, "xo");

Why is this necessary?

> +       if (IS_ERR(xo))
> +               return PTR_ERR(xo);
> +       clk_put(xo);
> +
> +       regmap = qcom_cc_map(pdev, &gpucc_msm8998_desc);
> +       if (IS_ERR(regmap))
> +               return PTR_ERR(regmap);
> +
> +       /* force periph logic on to acoid perf counter corruption */

avoid?

> +       regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13));
> +       /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
> +       regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
> +
> +       return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
> +}
> +

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