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Date:   Thu, 6 Jun 2019 14:29:45 +0100
From:   Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
To:     Amadeusz Sławiński 
        <amadeuszx.slawinski@...ux.intel.com>
Cc:     broonie@...nel.org, alsa-devel@...a-project.org,
        lgirdwood@...il.com, linux-kernel@...r.kernel.org, tiwai@...e.com
Subject: Re: [alsa-devel] [PATCH v2] ASoC: msm8916-wcd-digital: Add sidetone
 support



On 06/06/2019 14:24, Amadeusz Sławiński wrote:
>> +	SOC_SINGLE_SX_TLV("IIR1 INP1 Volume",
>> LPASS_CDC_IIR1_GAIN_B1_CTL,
>> +			0,  -84, 40, digital_gain),
>> +	SOC_SINGLE_SX_TLV("IIR1 INP2 Volume",
>> LPASS_CDC_IIR1_GAIN_B2_CTL,
>> +			0,  -84, 40, digital_gain),
>> +	SOC_SINGLE_SX_TLV("IIR1 INP3 Volume",
>> LPASS_CDC_IIR1_GAIN_B3_CTL,
>> +			0,  -84, 40, digital_gain),
>> +	SOC_SINGLE_SX_TLV("IIR1 INP4 Volume",
>> LPASS_CDC_IIR1_GAIN_B4_CTL,
>> +			0,  -84,	40, digital_gain),
> There seems to be some alignment issue in above line.
> And while I'm commenting this place, there is only 4 Volume controls,
> while there is 5 switches for IIR1 and IIR2, is this right?
> 

Each IIR Filter is 5 Stage, and IIR block is feed with 4 inputs, these 
volumes above refers to each input path.


Thanks,
srini
>> +	SOC_SINGLE_SX_TLV("IIR2 INP1 Volume",
>> LPASS_CDC_IIR2_GAIN_B1_CTL,

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