linux-kernel - Re: [PATCH 5/5] clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly

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Message-Id: <20190607210358.F21222146E@mail.kernel.org>
Date:   Fri, 07 Jun 2019 14:03:58 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Paul Cercueil <paul@...pouillou.net>
Cc:     linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        od@...c.me, Paul Cercueil <paul@...pouillou.net>
Subject: Re: [PATCH 5/5] clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly

Quoting Paul Cercueil (2019-05-02 14:25:02)
> The code was setting the bit 21 of the CPCCR register to use a divider
> of 2 for the "pll half" clock, and clearing the bit to use a divider
> of 1.
> 
> This is the opposite of how this register field works: a cleared bit
> means that the /2 divider is used, and a set bit means that the divider
> is 1.
> 
> Restore the correct behaviour using the newly introduced .div_table
> field.
> 
> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
> ---

Applied to clk-next