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Message-Id: <20190607212819.A5FAE208C3@mail.kernel.org>
Date: Fri, 07 Jun 2019 14:28:18 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
James Hogan <jhogan@...nel.org>,
Jason Cooper <jason@...edaemon.net>,
Jonathan Corbet <corbet@....net>,
Lee Jones <lee.jones@...aro.org>,
Marc Zyngier <marc.zyngier@....com>,
Mark Rutland <mark.rutland@....com>,
Michael Turquette <mturquette@...libre.com>,
Paul Burton <paul.burton@...s.com>,
Paul Cercueil <paul@...pouillou.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Rob Herring <robh+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: Mathieu Malaterre <malat@...ian.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-mips@...r.kernel.org,
linux-doc@...r.kernel.org, linux-clk@...r.kernel.org, od@...c.me,
Paul Cercueil <paul@...pouillou.net>
Subject: Re: [PATCH v12 05/13] clk: ingenic: Add driver for the TCU clocks
Quoting Paul Cercueil (2019-05-21 07:51:33)
> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
> index 34dc0da79c39..434893133eb4 100644
> --- a/drivers/clk/ingenic/Kconfig
> +++ b/drivers/clk/ingenic/Kconfig
> @@ -1,4 +1,4 @@
> -menu "Ingenic JZ47xx CGU drivers"
> +menu "Ingenic JZ47xx drivers"
> depends on MIPS
>
> config INGENIC_CGU_COMMON
> @@ -44,4 +44,13 @@ config INGENIC_CGU_JZ4780
>
> If building for a JZ4780 SoC, you want to say Y here.
>
> +config INGENIC_TCU_CLK
> + bool "Ingenic JZ47xx TCU clocks driver"
> + default MACH_INGENIC
> + depends on COMMON_CLK
Does the INGENIC_TCU_CLK config even exist if COMMON_CLK is disabled? I
suspect it's all part of the menuconfig so this depends is not useful?
> + select INGENIC_TCU
> + help
> + Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
> + JZ47xx SoCs.
> +
> endmenu
> diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c
> new file mode 100644
> index 000000000000..7249225a6994
> --- /dev/null
> +++ b/drivers/clk/ingenic/tcu.c
> @@ -0,0 +1,458 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * JZ47xx SoCs TCU clocks driver
> + * Copyright (C) 2019 Paul Cercueil <paul@...pouillou.net>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clockchips.h>
> +#include <linux/mfd/ingenic-tcu.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/ingenic,tcu.h>
> +
> +/* 8 channels max + watchdog + OST */
> +#define TCU_CLK_COUNT 10
> +
> +#define TCU_ERR(...) pr_crit("ingenic-tcu-clk: " __VA_ARGS__)
Why is it pr_crit instead of pr_err()?
> +
> +enum tcu_clk_parent {
> + TCU_PARENT_PCLK,
> + TCU_PARENT_RTC,
> + TCU_PARENT_EXT,
> +};
> +
[...]
> +
> +static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
> + unsigned int idx, enum tcu_clk_parent parent,
> + const struct ingenic_tcu_clk_info *info,
> + struct clk_hw_onecell_data *clocks)
> +{
> + struct ingenic_tcu_clk *tcu_clk;
> + int err;
> +
> + tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
> + if (!tcu_clk)
> + return -ENOMEM;
> +
> + tcu_clk->hw.init = &info->init_data;
> + tcu_clk->idx = idx;
> + tcu_clk->info = info;
> + tcu_clk->tcu = tcu;
> +
> + /* Reset channel and clock divider, set default parent */
> + ingenic_tcu_enable_regs(&tcu_clk->hw);
> + regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
> + ingenic_tcu_disable_regs(&tcu_clk->hw);
> +
> + err = clk_hw_register(NULL, &tcu_clk->hw);
> + if (err)
> + goto err_free_tcu_clk;
> +
> + err = clk_hw_register_clkdev(&tcu_clk->hw, info->init_data.name, NULL);
Do you have a use for clkdev? If DT lookups work just as well it would
be better to skip clkdev registration.
> + if (err)
> + goto err_clk_unregister;
> +
> + clocks->hws[idx] = &tcu_clk->hw;
> +
> + return 0;
> +
> +err_clk_unregister:
> + clk_hw_unregister(&tcu_clk->hw);
> +err_free_tcu_clk:
> + kfree(tcu_clk);
> + return err;
> +}
> +
> +static const struct ingenic_soc_info jz4740_soc_info = {
> + .num_channels = 8,
> + .has_ost = false,
> + .has_tcu_clk = true,
> +};
> +
> +static const struct ingenic_soc_info jz4725b_soc_info = {
> + .num_channels = 6,
> + .has_ost = true,
> + .has_tcu_clk = true,
> +};
> +
> +static const struct ingenic_soc_info jz4770_soc_info = {
> + .num_channels = 8,
> + .has_ost = true,
> + .has_tcu_clk = false,
> +};
> +
> +static const struct of_device_id ingenic_tcu_of_match[] __initconst = {
> + { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
> + { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
> + { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
> + { }
> +};
> +
> +static int __init ingenic_tcu_probe(struct device_node *np)
> +{
> + const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
> + struct ingenic_tcu *tcu;
> + struct regmap *map;
> + unsigned int i;
> + int ret;
> +
> + map = ingenic_tcu_get_regmap(np);
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
> + if (!tcu)
> + return -ENOMEM;
> +
> + tcu->map = map;
> + tcu->soc_info = id->data;
> +
> + if (tcu->soc_info->has_tcu_clk) {
> + tcu->clk = of_clk_get_by_name(np, "tcu");
Is this clk necessary to read/write registers in this clk driver? And
this clk isn't the parent of the clks? Why is it managed by Linux at
all? Will there be a time when it's turned off?
I'm asking because it looks like we're calling clk APIs from within clk
provider implementation. That works right now because of our locking
scheme, but this will put up another roadblock to making the prepare and
enable locks not recursive. I've seen some drivers take an approach of
enabling the clk when the provider is PM runtime active, and disable the
clk when the provider is runtime PM inactive. This gets it out of the
provider path and into the runtime PM path. If you take that approach
then when we move the runtime PM code in clk core outside of the prepare
lock we should be able to avoid any recursive locking scenarios.
> + if (IS_ERR(tcu->clk)) {
> + ret = PTR_ERR(tcu->clk);
> + TCU_ERR("Cannot get TCU clock\n");
> + goto err_free_tcu;
> + }
> +
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