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Date:   Mon, 10 Jun 2019 07:51:32 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Niklas Cassel <niklas.cassel@...aro.org>,
        Tengfei Fan <tengfeif@...eaurora.org>
Cc:     Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        MSM <linux-arm-msm@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] pinctrl: qcom: Clear status bit on irq_unmask

Quoting Linus Walleij (2019-06-07 14:08:10)
> On Fri, May 31, 2019 at 8:52 AM Tengfei Fan <tengfeif@...eaurora.org> wrote:
> 
> > The gpio interrupt status bit is getting set after the
> > irq is disabled and causing an immediate interrupt after
> > enablling the irq, so clear status bit on irq_unmask.
> >
> > Signed-off-by: Tengfei Fan <tengfeif@...eaurora.org>
> 
> This looks pretty serious, can one of the Qcom maintainers ACK
> this?
> 
> Should it be sent to fixes and even stable?
> 
> Fixes: tag?
> 

How is the interrupt status bit getting set after the irq is disabled?
It looks like this is a level type interrupt? I thought that after
commit b55326dc969e ("pinctrl: msm: Really mask level interrupts to
prevent latching") this wouldn't be a problem. Am I wrong, or is qcom
just clearing out patches on drivers and this is the last one that needs
to be upstreamed?

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