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Message-ID: <20190610192026.GI5488@zn.tnic>
Date: Mon, 10 Jun 2019 21:20:26 +0200
From: Borislav Petkov <bp@...en8.de>
To: Fenghua Yu <fenghua.yu@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, H Peter Anvin <hpa@...or.com>,
Ravi V Shankar <ravi.v.shankar@...el.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [RFC PATCH] x86/cpufeatures: Enumerate new AVX512 bfloat16
instructions
On Mon, Jun 10, 2019 at 10:02:38AM -0700, Fenghua Yu wrote:
> AVX512 Vector Neural Network Instructions (VNNI) in Intel Deep Learning
> Boost support bfloat16 format (BF16). BF16 is a short version of FP32 and
> has several advantages over FP16. BF16 offers more than enough range for
> deep learning training tasks and doesn't need to handle hardware exception
> as this is a performance optimization. FP32 accumulation after the
> multiply is essential to achieve sufficient numerical behavior on an
> application level.
>
> AVX512 bfloat16 instructions can be enumerated by:
> CPUID.(EAX=7,ECX=1):EAX[bit 5] AVX512_BF16
>
> Detailed information of the CPUID bit and AVX512 bfloat16 instructions
> can be found in the latest Intel Architecture Instruction Set Extensions
> and Future Features Programming Reference.
>
> Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
> ---
>
> Since split lock feature (to-be-upstreamed) occupies the last bit
> of word 7, need to create a new word 19 to host AVX512_BF16 and other
> future features.
Is CPUID.(EAX=7,ECX=1):EAX going to contain only feature bits? If so,
just make it a proper feature word instead of a linux-specific one.
Also, while on the subject, you can recycle word 11
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
and move it to scattered as it is a complete waste. Word 12 too, for
that matter. But do that in separate patches.
Thx.
--
Regards/Gruss,
Boris.
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