linux-kernel - Re: [PATCHv5 2/2] mtd: spi-nor: cadence-quadspi: add reset control

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Wed, 12 Jun 2019 16:12:10 -0500
From:   Dinh Nguyen <dinguyen@...nel.org>
To:     Tudor.Ambarus@...rochip.com, linux-mtd@...ts.infradead.org
Cc:     marex@...x.de, dwmw2@...radead.org, computersforpeace@...il.com,
        bbrezillon@...nel.org, linux-kernel@...r.kernel.org,
        tien.fong.chee@...el.com
Subject: Re: [PATCHv5 2/2] mtd: spi-nor: cadence-quadspi: add reset control



On 6/12/19 10:07 AM, Tudor.Ambarus@...rochip.com wrote:
> 
> 
> On 06/12/2019 05:37 PM, Dinh Nguyen wrote:
>> External E-Mail
>>
>>
>> Get the reset control properties for the QSPI controller and bring them
>> out of reset. Most will have just one reset bit, but there is an additional
>> OCP reset bit that is used ECC. The OCP reset bit will also need to get
>> de-asserted as well. [1]
>>
>> The reason this patch is needed is in the case where a bootloader leaves
>> the QSPI controller in a reset state, or a state where init cannot occur
>> successfully, this patch will put the QSPI controller into a clean state.
>>
>> [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html
>>
>> Suggested-by: Tien-Fong Chee <tien.fong.chee@...el.com>
>> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
>> ---
>> v5: remove udelay(not needed) on tested hardware
>>     group reset assert/deassert together
>>     update commit message with reasoning for patch
>> v4: fix compile error
>> v3: return full error by using PTR_ERR(rtsc)
>>     move reset control calls until after the clock enables
>>     use udelay(2) to be safe
>>     Add optional OCP(Open Core Protocol) reset signal
>> v2: use devm_reset_control_get_optional_exclusive
>>     print an error message
>>     return -EPROBE_DEFER
>> ---
>>  drivers/mtd/spi-nor/cadence-quadspi.c | 26 ++++++++++++++++++++++++++
>>  1 file changed, 26 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index 792628750eec..f8b1009e488c 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -34,6 +34,7 @@
>>  #include <linux/of.h>
>>  #include <linux/platform_device.h>
>>  #include <linux/pm_runtime.h>
>> +#include <linux/reset.h>
>>  #include <linux/sched.h>
>>  #include <linux/spi/spi.h>
>>  #include <linux/timer.h>
>> @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev)
>>  	struct cqspi_st *cqspi;
>>  	struct resource *res;
>>  	struct resource *res_ahb;
>> +	struct reset_control *rstc;
>> +	struct reset_control *rstc_ocp;
>>  	const struct cqspi_driver_platdata *ddata;
>>  	int ret;
>>  	int irq;
>> @@ -1402,6 +1405,29 @@ static int cqspi_probe(struct platform_device *pdev)
>>  		goto probe_clk_failed;
>>  	}
>>  
>> +	/* Obtain QSPI reset control */
>> +	rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
>> +	if (IS_ERR(rstc)) {
>> +		dev_err(dev, "Cannot get QSPI reset.\n");
>> +		return PTR_ERR(rstc);
>> +	}
>> +
>> +	rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
>> +	if (IS_ERR(rstc_ocp)) {
>> +		dev_err(dev, "Cannot get QSPI OCP reset.\n");
>> +		return PTR_ERR(rstc_ocp);
>> +	}
>> +
>> +	if (rstc) {
> 
> Hi, Dinh,
> 
> reset_control_assert/deassert() already have checks for null, you can call them
> directly without checking for null.
> 
>> +		reset_control_assert(rstc);
>> +		reset_control_deassert(rstc);
> 
> Is there any difference between:
> reset_control_assert(rstc);
> reset_control_assert(rstc_ocp);
> 
> reset_control_deassert(rstc);
> reset_control_deassert(rstc_ocp);
> 
> and:
> 
> reset_control_assert(rstc);
> reset_control_deassert(rstc);
> 
> reset_control_assert(rstc_ocp);
> reset_control_deassert(rstc_ocp);
> 
> Which one would you choose?
> 

I prefer grouping the assert/deassert for each reset pointer together.

Dinh