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Message-ID: <20190612095339.20118-13-vidyas@nvidia.com>
Date: Wed, 12 Jun 2019 15:23:36 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <lorenzo.pieralisi@....com>, <bhelgaas@...gle.com>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<thierry.reding@...il.com>, <jonathanh@...dia.com>,
<kishon@...com>, <catalin.marinas@....com>, <will.deacon@....com>,
<jingoohan1@...il.com>, <gustavo.pimentel@...opsys.com>
CC: <digetx@...il.com>, <mperttunen@...dia.com>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <kthota@...dia.com>,
<mmaddireddy@...dia.com>, <vidyas@...dia.com>, <sagar.tv@...il.com>
Subject: [PATCH V10 12/15] arm64: tegra: Enable PCIe slots in P2972-0000 board
Enable PCIe controller nodes to enable respective PCIe slots on
P2972-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes since [v6]:
* None
Changes since [v5]:
* Arranged PCIe nodes in the order of their addresses
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed P2U label names to reflect new format that includes 'hsio'/'nvhs'
strings to reflect UPHY brick they belong to
Changes since [v1]:
* Dropped 'pcie-' from phy-names property strings
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
.../boot/dts/nvidia/tegra194-p2972-0000.dts | 41 +++++++++++++++++++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 9f5810765efc..62e07e1197cc 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -191,7 +191,7 @@
regulator-boot-on;
};
- sd3 {
+ vdd_1v8ao: sd3 {
regulator-name = "VDD_1V8AO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index 6e6df650a4b0..eb79663b2af8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -167,4 +167,45 @@
};
};
};
+
+ pcie@...00000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_hsio_0>;
+ phy-names = "p2u-0";
+ };
+
+ pcie@...40000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_hsio_7>;
+ phy-names = "p2u-0";
+ };
+
+ pcie@...80000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
+ <&p2u_hsio_5>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+
+ pcie@...a0000 {
+ status = "disabled";
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
};
--
2.17.1
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