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Message-ID: <20190612142917.sbpks6nhf7fy6rk6@M43218.corp.atmel.com>
Date:   Wed, 12 Jun 2019 16:29:17 +0200
From:   Ludovic Desroches <ludovic.desroches@...rochip.com>
To:     Nicolas Ferre - M43238 <Nicolas.Ferre@...rochip.com>
CC:     Codrin Ciubotariu - M19940 <Codrin.Ciubotariu@...rochip.com>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        "alexandre.belloni@...tlin.com" <alexandre.belloni@...tlin.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: at91: generated: Truncate divisor to
 GENERATED_MAX_DIV + 1

On Wed, Jun 12, 2019 at 03:54:00PM +0200, Nicolas Ferre - M43238 wrote:
> On 10/06/2019 at 17:20, Codrin Ciubotariu - M19940 wrote:
> > From: Codrin Ciubotariu <codrin.ciubotariu@...rochip.com>
> > 
> > In clk_generated_determine_rate(), if the divisor is greater than
> > GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned.
> > If clk_generated_set_rate() will be called later with this wrong
> > rate, it will return -EINVAL, so the generated clock won't change
> > its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1.
> > 
> > Fixes: 8c7aa6328947 ("clk: at91: clk-generated: remove useless divisor loop")
> > Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@...rochip.com>
> 
> Yes:
> Acked-by: Nicolas Ferre <nicolas.ferre@...rochip.com>

Acked-by: Ludovic Desroches <ludovic.desroches@...rochip.com>

Thanks

Ludovic

> 
> Thanks for having fixed this Codrin. Best regards,
>    Nicolas
> 
> > ---
> >   drivers/clk/at91/clk-generated.c | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> > index 5f18847965c1..290cffe35deb 100644
> > --- a/drivers/clk/at91/clk-generated.c
> > +++ b/drivers/clk/at91/clk-generated.c
> > @@ -146,6 +146,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> >   			continue;
> >   
> >   		div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
> > +		if (div > GENERATED_MAX_DIV + 1)
> > +			div = GENERATED_MAX_DIV + 1;
> >   
> >   		clk_generated_best_diff(req, parent, parent_rate, div,
> >   					&best_diff, &best_rate);
> > 
> 
> 
> -- 
> Nicolas Ferre

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