linux-kernel - Re: [PATCH 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width

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Message-ID: <94fa2a5e-e96d-acb3-46c2-5f6b1dea6711@intel.com>
Date:   Thu, 13 Jun 2019 11:40:14 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Raul Rangel <rrangel@...omium.org>
Cc:     linux-mmc@...r.kernel.org, ernest.zhang@...hubtech.com,
        djkurtz@...omium.org, linux-kernel@...r.kernel.org,
        Ulf Hansson <ulf.hansson@...aro.org>
Subject: Re: [PATCH 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller
 supports 8-bit width

On 12/06/19 6:08 PM, Raul Rangel wrote:
> On Wed, Jun 12, 2019 at 04:09:47PM +0300, Adrian Hunter wrote:
>> On 10/06/19 9:53 PM, Raul E Rangel wrote:
>>> The O2 controller supports 8-bit EMMC access. mmc_select_bus_width()
>>> will be used to determine if the MMC supports 8-bit or 4-bit access.
>>
>> The problem is that the bit indicates a host controller capability, not how
>> many data lines there actually are on the board.  Will this break something
>> that does not have 8 lines?
> 
> So I asked the controller vendor about that:
>> The capability shows the host controller can support 1,4,and 8 bit bus
>> data transfer but it also depends on if HW can support it. Driver or FW
>> should implement the bus testing procedure that is defined in A.6.3.a
>> in JESD84-B51 spec to decide the real bus width that is supported in HW.
> 
> This seems to be what `mmc_select_bus_width()` is doing.

Good point.  Can you add this information to the commit message and add a
comment in the code.

> 
> I don't actually have any 4-bit hardware to test with though.
> 
> Thanks for the review!
>