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Message-ID: <alpine.DEB.2.21.1906142253230.1760@nanos.tec.linutronix.de>
Date: Fri, 14 Jun 2019 22:53:40 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Borislav Petkov <bp@...en8.de>
cc: LKML <linux-kernel@...r.kernel.org>,
Adric Blake <promarbler14@...il.com>,
Peter Zijlstra <peterz@...radead.org>, x86@...nel.org
Subject: Re: [PATCH] x86/microcode, cpuhotplug: Add a microcode loader CPU
hotplug callback
On Fri, 14 Jun 2019, Borislav Petkov wrote:
> From: Borislav Petkov <bp@...e.de>
>
> Adric Blake reported the following warning during suspend-resume:
>
> Enabling non-boot CPUs ...
> x86: Booting SMP configuration:
> smpboot: Booting Node 0 Processor 1 APIC 0x2
> unchecked MSR access error: WRMSR to 0x10f (tried to write 0x0000000000000000) \
> at rIP: 0xffffffff8d267924 (native_write_msr+0x4/0x20)
> Call Trace:
> intel_set_tfa
> intel_pmu_cpu_starting
> ? x86_pmu_dead_cpu
> x86_pmu_starting_cpu
> cpuhp_invoke_callback
> ? _raw_spin_lock_irqsave
> notify_cpu_starting
> start_secondary
> secondary_startup_64
> microcode: sig=0x806ea, pf=0x80, revision=0x96
> microcode: updated to revision 0xb4, date = 2019-04-01
> CPU1 is up
>
> The MSR in question is MSR_TFA_RTM_FORCE_ABORT and that MSR is emulated
> by microcode. The log above shows that the microcode loader callback
> happens after the PMU restoration, leading to the conjecture that
> because the microcode hasn't been updated yet, that MSR is not present
> yet, leading to the #GP.
>
> Add a microcode loader-specific hotplug vector which comes before
> the PERF vectors and thus executes earlier and makes sure the MSR is
> present.
>
> Fixes: 400816f60c54 ("perf/x86/intel: Implement support for TSX Force Abort")
> Reported-by: Adric Blake <promarbler14@...il.com>
> Signed-off-by: Borislav Petkov <bp@...e.de>
> Cc: Peter Zijlstra <peterz@...radead.org>
> Cc: Thomas Gleixner <tglx@...utronix.de>
> Cc: x86@...nel.org
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=203637
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
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