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Message-Id: <20190614095309.24100-12-l.luba@partner.samsung.com>
Date: Fri, 14 Jun 2019 11:53:07 +0200
From: Lukasz Luba <l.luba@...tner.samsung.com>
To: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...nel.org,
b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
cw00.choi@...sung.com, kyungmin.park@...sung.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com,
myungjoo.ham@...sung.com, keescook@...omium.org, tony@...mide.com,
jroedel@...e.de, treding@...dia.com, digetx@...il.com,
gregkh@...uxfoundation.org, willy.mh.wolff.ml@...il.com,
Lukasz Luba <l.luba@...tner.samsung.com>
Subject: [PATCH v10 11/13] ARM: dts: exynos: add syscon to clock compatible
In order to get the clock by phandle and use it with regmap it needs to be
compatible with syscon. The DMC driver uses two registers from clock
register set and needs the regmap of them.
Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 2 +-
arch/arm/boot/dts/exynos5800.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..d153617ff1a3 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -173,7 +173,7 @@
};
clock: clock-controller@...10000 {
- compatible = "samsung,exynos5420-clock";
+ compatible = "samsung,exynos5420-clock", "syscon";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319fd65..0a2b3287ed92 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,7 +17,7 @@
};
&clock {
- compatible = "samsung,exynos5800-clock";
+ compatible = "samsung,exynos5800-clock", "syscon";
};
&cluster_a15_opp_table {
--
2.17.1
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