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Message-ID: <20190614132122.GA3629@krava>
Date:   Fri, 14 Jun 2019 15:21:22 +0200
From:   Jiri Olsa <jolsa@...hat.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     Jiri Olsa <jolsa@...nel.org>,
        "Liang, Kan" <kan.liang@...ux.intel.com>,
        Stephane Eranian <eranian@...gle.com>,
        Andy Lutomirski <luto@...nel.org>,
        lkml <linux-kernel@...r.kernel.org>,
        Ingo Molnar <mingo@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Vince Weaver <vincent.weaver@...ne.edu>,
        Thomas Gleixner <tglx@...utronix.de>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: [PATCHv2 0/8] perf/x86: Rework msr probe interface

On Fri, Jun 14, 2019 at 02:37:15PM +0200, Peter Zijlstra wrote:
> On Fri, Jun 14, 2019 at 12:20:46PM +0200, Jiri Olsa wrote:
> > On Fri, May 31, 2019 at 02:09:50PM +0200, Jiri Olsa wrote:
> > > hi,
> > > following up on [1], [2] and [3], this patchset adds update
> > > attribute groups to pmu, factors out the MSR probe code and
> > > use it in msr,cstate* and rapl PMUs.
> > > 
> > > The functionality stays the same with one exception:
> > > for msr PMU: the event is not exported if the rdmsr return zero
> > > on event's msr, cstate* and rapl pmu functionality stays.
> > > 
> > > And also: ;-)
> > > > Somewhere along the line you lost the explanation of _why_ we're doing
> > > > this; namely: virt sucks.
> > > 
> > > Also available in:
> > >   git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git
> > >   perf/msr
> > > 
> > > Tested on snb and skylake servers.
> > > 
> > > v2 changes:
> > >   - checking zero rdmsr only for msr PMU events,
> > >     cstate* and rapl pmu functionality stays unchanged
> > 
> > ping
> 
> I was waiting a new post because you mentioned something about some
> people not being happy with this, something about a wonky BIOS failing
> this on native.

ah, nope, that's unrelated.. I sent RFC about that today:
  [RFC] perf/x86/intel: Disable check_msr for real hw

but while checking on this one, I realized I need to send v3 ;-)

jirka

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