linux-kernel - Re: [PATCH v2 0/3] Add support for Zhaoxin Processors

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Message-ID: <alpine.DEB.2.21.1906141705400.1722@nanos.tec.linutronix.de>
Date:   Fri, 14 Jun 2019 17:06:57 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Tony W Wang-oc <TonyWWang-oc@...oxin.com>
cc:     "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "rjw@...ysocki.net" <rjw@...ysocki.net>,
        "lenb@...nel.org" <lenb@...nel.org>,
        David Wang <DavidWang@...oxin.com>,
        "Cooper Yan(BJ-RD)" <CooperYan@...oxin.com>,
        "Qiyuan Wang(BJ-RD)" <QiyuanWang@...oxin.com>,
        "Herry Yang(BJ-RD)" <HerryYang@...oxin.com>
Subject: Re: [PATCH v2 0/3] Add support for Zhaoxin Processors

Tony,

On Tue, 28 May 2019, Tony W Wang-oc wrote:

> As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
>  ("Zhaoxin") provide high performance general-purpose x86 processors.
> 
> CPU Vendor ID "Shanghai" belongs to Zhaoxin.
> 
> To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
> type (X86_VENDOR_ZHAOXIN, with value of 10) in
> arch/x86/include/asm/processor.h.
> 
> To enable the support of Linux kernel's specific configuration to
> Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
> 
> This patch series have been applied and tested successfully on Zhaoxin's
> Soc silicon. Also tested on other processors, it works fine and makes no
> harm to the existing codes.
> 
> v1->v2:
>  - Rebased on 5.2.0-rc2 and tested against it.
>  - remove GPL "boilerplate" text in the patch.
>  - adjust signed-off-by: line match From: line.
>  - run patch series through checkpatch.pl.
> 
> v1:
>  - Rebased on 5.2.0-rc1 and tested against it.
>  - Split the patch set to small series of patches.
>  - Rework patch descriptions.
> 
> TonyWWang (3):
>  x86/cpu: Create Zhaoxin processors architecture support file
>  ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
>  x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
>  in C3

I only got 0/3 and 1/3 of Version 2. Please always send the complete set.

Thanks,

	tglx