linux-kernel - Re: [PATCH v3 2/5] crypto: caam - correct DMA address size for the i.MX8

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Message-ID: <VI1PR04MB5055A9A725CED589FCF9254DEEEB0@VI1PR04MB5055.eurprd04.prod.outlook.com>
Date:   Mon, 17 Jun 2019 19:24:25 +0000
From:   Leonard Crestez <leonard.crestez@....com>
To:     Andrey Smirnov <andrew.smirnov@...il.com>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        Horia Geanta <horia.geanta@....com>
CC:     Chris Spencer <christopher.spencer@....co.uk>,
        Aymen Sghaier <aymen.sghaier@....com>,
        Franck Lenormand <franck.lenormand@....com>,
        Cory Tusar <cory.tusar@....aero>,
        Chris Healy <cphealy@...il.com>,
        Lucas Stach <l.stach@...gutronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Iuliana Prodan <iuliana.prodan@....com>
Subject: Re: [PATCH v3 2/5] crypto: caam - correct DMA address size for the
 i.MX8

On 6/17/2019 7:04 PM, Andrey Smirnov wrote:
> From: Chris Spencer <christopher.spencer@....co.uk>
> 
> The i.MX8 is arm64, but its CAAM DMA address size is 32-bits.

> +/*
> + * On i.MX8 boards the arch is arm64 but the CAAM dma address size is
> + * 32 bits on 8MQ and 36 bits on 8QM and 8QXP.
> + * For 8QM and 8QXP there is a configurable field PS called pointer size
> + * in the MCFGR register to switch between 32 and 64 (default 32)
> + * But this register is only accessible by the SECO and is left to its
> + * default value.
> + * Here we set the CAAM dma address size to 32 bits for all i.MX8
> + */
> +#if defined(CONFIG_ARM64) && defined(CONFIG_ARCH_MXC)
> +#define caam_dma_addr_t u32
> +#else
> +#define caam_dma_addr_t dma_addr_t
> +#endif

Wait, doesn't this break Layerscape? Support for multiple SOC families 
can be enabled at the same time and it is something that we actually 
want to support.

--
Regards,
Leonard