lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <e0e1b708-7dd4-a58a-7906-05bf3065cbda@gmail.com>
Date:   Mon, 17 Jun 2019 17:04:21 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Jon Hunter <jonathanh@...dia.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Joseph Lo <josephl@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>
Cc:     linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/6] clocksource/drivers/tegra: Set and use timer's
 period

17.06.2019 13:51, Jon Hunter пишет:
> 
> On 14/06/2019 17:45, Dmitry Osipenko wrote:
>> 14.06.2019 18:48, Jon Hunter пишет:
>>>
>>> On 10/06/2019 17:43, Dmitry Osipenko wrote:
>>>> The of_clk structure has a period field that is set up initially by
>>>> timer_of_clk_init(), that period value need to be adjusted for a case of
>>>> TIMER1-9 that are running at a fixed rate that doesn't match the clock's
>>>> rate. Note that the period value is currently used only by some of the
>>>> clocksource drivers internally and hence this is just a minor cleanup
>>>> change that doesn't fix anything.
>>>>
>>>> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
>>>> ---
>>>>  drivers/clocksource/timer-tegra.c | 5 +++--
>>>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c
>>>> index 810b4e7435cf..646b3530c2d2 100644
>>>> --- a/drivers/clocksource/timer-tegra.c
>>>> +++ b/drivers/clocksource/timer-tegra.c
>>>> @@ -71,9 +71,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt)
>>>>  static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>>  {
>>>>  	void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>> +	unsigned long period = timer_of_period(to_timer_of(evt));
>>>>  
>>>> -	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER |
>>>> -		       ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>>>> +	writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
>>>>  		       reg_base + TIMER_PTV);
>>>>  
>>>>  	return 0;
>>>> @@ -297,6 +297,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20,
>>>>  		cpu_to->clkevt.rating = rating;
>>>>  		cpu_to->clkevt.cpumask = cpumask_of(cpu);
>>>>  		cpu_to->of_base.base = timer_reg_base + base;
>>>> +		cpu_to->of_clk.period = DIV_ROUND_UP(rate, HZ);
>>>
>>> Any reason you made this a round-up?
>>
>> That's what timer_of_clk_init() does, I assume it should be a more correct variant.
> 
> Sounds to me like this should be 2 patches, because you are changing the
> value. This is not just purely cleanup IMO.

Indeed, that could be at least mentioned in the commit message. Probably I just
assumed that this is such a minor change that not worth anything. A hundred of
microseconds is hardly noticeable.

I'm not really sure if this really worth a re-spin at this point. Jon, are you insisting?

Also, I now see that some drivers use DIV_ROUND_CLOSEST(), maybe it will be even
better? Not sure.. given that this is still a microseconds difference.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ