[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <201906172050.AA52A49E9@keescook>
Date: Mon, 17 Jun 2019 21:09:09 -0700
From: Kees Cook <keescook@...omium.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>, x86@...nel.org,
Peter Zijlstra <peterz@...radead.org>,
Dave Hansen <dave.hansen@...el.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] x86/asm: Pin sensitive CR4 bits
On Mon, Jun 17, 2019 at 12:26:01AM +0200, Thomas Gleixner wrote:
> Nah. The straight forward approach is to do right when the secondary CPU
> comes into life, before it does any cr4 write (except for the code in
> entry_64.S), something like the below.
Okay, will do; thanks! :) I'll respin things and get it tested.
--
Kees Cook
Powered by blists - more mailing lists