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Message-ID: <40d77b71-efdd-08e6-3d66-743ab0623906@microchip.com>
Date:   Tue, 18 Jun 2019 09:10:24 +0000
From:   <Tudor.Ambarus@...rochip.com>
To:     <dinguyen@...nel.org>, <robh@...nel.org>
CC:     <linux-mtd@...ts.infradead.org>, <marex@...x.de>,
        <bbrezillon@...nel.org>, <linux-kernel@...r.kernel.org>,
        <computersforpeace@...il.com>, <dwmw2@...radead.org>,
        <devicetree@...r.kernel.org>
Subject: Re: [PATCHv6 1/2] dt-bindings: cadence-quadspi: add options reset
 property

+Rob, devicetree@...r.kernel.org

Hi, Rob,

Dinh forgot to send this to the device tree mailing list. Would you please
review it?

Thanks,
ta

On 06/13/2019 02:31 PM, Dinh Nguyen wrote:
> External E-Mail
> 
> 
> The QSPI module can have an optional reset signals that will hold the
> module in a reset state.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
> ---
> v6: no change
> v5: document reset-names
> v4: no change
> v3: created base on review comments
> v2: did not exist
> v1: did not exist
> ---
>  Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> index 4345c3a6f530..945be7d5b236 100644
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> @@ -35,6 +35,9 @@ custom properties:
>  		  (qspi_n_ss_out).
>  - cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
>                    and first bit transfer.
> +- resets	: Must contain an entry for each entry in reset-names.
> +		  See ../reset/reset.txt for details.
> +- reset-names	: Must include either "qspi" and/or "qspi-ocp".
>  
>  Example:
>  
> @@ -50,6 +53,8 @@ Example:
>  		cdns,fifo-depth = <128>;
>  		cdns,fifo-width = <4>;
>  		cdns,trigger-address = <0x00000000>;
> +		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> +		reset-names = "qspi", "qspi-ocp";
>  
>  		flash0: n25q00@0 {
>  			...
> 

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