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Message-ID: <20190618114046.GG28892@ulmo>
Date:   Tue, 18 Jun 2019 13:40:46 +0200
From:   Thierry Reding <thierry.reding@...il.com>
To:     Sowjanya Komatineni <skomatineni@...dia.com>
Cc:     jonathanh@...dia.com, tglx@...utronix.de, jason@...edaemon.net,
        marc.zyngier@....com, linus.walleij@...aro.org, stefan@...er.ch,
        mark.rutland@....com, pdeschrijver@...dia.com, pgaikwad@...dia.com,
        sboyd@...nel.org, linux-clk@...r.kernel.org,
        linux-gpio@...r.kernel.org, jckuo@...dia.com, josephl@...dia.com,
        talho@...dia.com, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, mperttunen@...dia.com,
        spatra@...dia.com, robh+dt@...nel.org, digetx@...il.com,
        devicetree@...r.kernel.org
Subject: Re: [PATCH V3 04/17] clk: tegra: save and restore divider rate

On Tue, Jun 18, 2019 at 12:46:18AM -0700, Sowjanya Komatineni wrote:
> This patch implements context save and restore for clock divider.
> 
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
> 
> So during suspend entry the context of clock divider is saved and
> on resume context is restored back for normal operation.
> 
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---
>  drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++
>  drivers/clk/tegra/clk.h         |  2 ++
>  2 files changed, 25 insertions(+)

Acked-by: Thierry Reding <treding@...dia.com>

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