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Message-ID: <50a5120f512e7d6784efa403a7597c159074c8c1.camel@synopsys.com>
Date: Thu, 20 Jun 2019 18:34:29 +0000
From: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
To: "peterz@...radead.org" <peterz@...radead.org>,
"Vineet.Gupta1@...opsys.com" <Vineet.Gupta1@...opsys.com>
CC: "jbaron@...hat.com" <jbaron@...hat.com>,
"linux-snps-arc@...ts.infradead.org"
<linux-snps-arc@...ts.infradead.org>,
Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Eugeniy.Paltsev@...opsys.com" <Eugeniy.Paltsev@...opsys.com>,
"pbonzini@...hat.com" <pbonzini@...hat.com>,
"ard.biesheuvel@...aro.org" <ard.biesheuvel@...aro.org>
Subject: Re: [PATCH] ARC: ARCv2: jump label: implement jump label patching
Hi Peter,
On Wed, 2019-06-19 at 10:12 +0200, Peter Zijlstra wrote:
> On Tue, Jun 18, 2019 at 04:16:20PM +0000, Vineet Gupta wrote:
>
> > > +/*
> > > + * To make atomic update of patched instruction available we need to guarantee
> > > + * that this instruction doesn't cross L1 cache line boundary.
> > > + *
>
> Oh urgh. Is that the only way ARC can do text patching? We've actually
> considered something like this on x86 at some point, but there we have
> the 'fun' detail that the i-fetch window does not in fact align with L1
> size on all uarchs, so that got complicated real fast.
>
> I'm assuming you've looked at what x86 currently does and found
> something like that doesn't work for ARC?
To be honest I've mostly look at arm/arm64 implementation :)
But yeah it's good remark about i-fetch window.
It's named 'instruction_fetch_block_width' in ARC documentation and it's
smaller than L1 I$ line size. On ARCv2 it's 16 byte.
So in current implementation we need to guarantee that this instruction doesn't
cross 'instruction_fetch_block' and not L1 cache line boundary.
So there is no problem with this code itself but the comment should be fixed.
[snip]
--
Eugeniy Paltsev
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