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Message-Id: <1561029712-11848-2-git-send-email-jing2.liu@linux.intel.com>
Date: Thu, 20 Jun 2019 19:21:52 +0800
From: Jing Liu <jing2.liu@...ux.intel.com>
To: pbonzini@...hat.com, kvm@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, jing2.liu@...el.com,
jing2.liu@...ux.intel.com
Subject: [PATCH RFC] kvm: x86: Expose AVX512_BF16 feature to guest
AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
format (BF16) for deep learning optimization.
Intel adds AVX512 BFLOAT16 feature in CooperLake, which is CPUID.7.1.EAX[5].
Detailed information of the CPUID bit can be found here,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf.
Signed-off-by: Jing Liu <jing2.liu@...ux.intel.com>
---
arch/x86/kvm/cpuid.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e18a9f9..10be53f 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -484,6 +484,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
entry->edx = 0;
break;
case 7: {
+ int i, times = entry->eax;
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
/* Mask ebx against host capability word 9 */
if (index == 0) {
@@ -507,12 +508,23 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
* if the host doesn't support it.
*/
entry->edx |= F(ARCH_CAPABILITIES);
- } else {
+ } else if (index > times) {
+ entry->eax = 0;
entry->ebx = 0;
entry->ecx = 0;
entry->edx = 0;
}
- entry->eax = 0;
+ for (i = 1; i <= times; i++) {
+ if (*nent >= maxnent)
+ goto out;
+ do_cpuid_1_ent(&entry[i], function, i);
+ entry[i].eax &= F(AVX512_BF16);
+ entry[i].ebx = 0;
+ entry[i].ecx = 0;
+ entry[i].edx = 0;
+ entry[i].flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+ ++*nent;
+ }
break;
}
case 9:
--
1.8.3.1
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