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Message-ID: <alpine.DEB.2.21.1906211732330.5503@nanos.tec.linutronix.de>
Date: Fri, 21 Jun 2019 17:33:28 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Jacob Pan <jacob.jun.pan@...el.com>
cc: Stephane Eranian <eranian@...gle.com>,
Kate Stewart <kstewart@...uxfoundation.org>,
Peter Zijlstra <peterz@...radead.org>,
Jan Kiszka <jan.kiszka@...mens.com>,
Ricardo Neri <ricardo.neri@...el.com>,
Ingo Molnar <mingo@...nel.org>,
Wincy Van <fanwenyi0529@...il.com>,
Ashok Raj <ashok.raj@...el.com>, x86 <x86@...nel.org>,
Andi Kleen <andi.kleen@...el.com>,
Borislav Petkov <bp@...e.de>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
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Tony Luck <tony.luck@...el.com>,
Randy Dunlap <rdunlap@...radead.org>,
LKML <linux-kernel@...r.kernel.org>,
iommu@...ts.linux-foundation.org,
Philippe Ombredanne <pombredanne@...b.com>
Subject: Re: [RFC PATCH v4 20/21] iommu/vt-d: hpet: Reserve an interrupt
remampping table entry for watchdog
On Wed, 19 Jun 2019, Jacob Pan wrote:
> On Tue, 18 Jun 2019 01:08:06 +0200 (CEST)
> Thomas Gleixner <tglx@...utronix.de> wrote:
> >
> > Unless this problem is not solved and I doubt it can be solved after
> > talking to IOMMU people and studying manuals,
>
> I agree. modify irte might be done with cmpxchg_double() but the queued
> invalidation interface for IRTE cache flush is shared with DMA and
> requires holding a spinlock for enque descriptors, QI tail update etc.
>
> Also, reserving & manipulating IRTE slot for hpet via backdoor might not
> be needed if the HPET PCI BDF (found in ACPI) can be utilized. But it
> might need more work to add a fake PCI device for HPET.
What would PCI/BDF solve?
Thanks,
tglx
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