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Date: Sun, 23 Jun 2019 12:38:00 +0800 From: Icenowy Zheng <icenowy@...c.io> To: Rob Herring <robh+dt@...nel.org>, Maxime Ripard <maxime.ripard@...tlin.com>, Chen-Yu Tsai <wens@...e.org>, Linus Walleij <linus.walleij@...aro.org> Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org, linux-sunxi@...glegroups.com, Icenowy Zheng <icenowy@...c.io> Subject: [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@...c.io> --- No changes in v3. Patch introduced in v2. Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..48c126a7a848 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -353,6 +353,11 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: allwinner,sun8i-s3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino -- 2.21.0
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