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Message-ID: <20190624180634.GB7292@krava>
Date: Mon, 24 Jun 2019 20:06:34 +0200
From: Jiri Olsa <jolsa@...hat.com>
To: Andi Kleen <ak@...ux.intel.com>
Cc: Peter Zijlstra <peterz@...radead.org>,
Kan Liang <kan.liang@...el.com>, Jiri Olsa <jolsa@...nel.org>,
David Carrillo-Cisneros <davidcc@...gle.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
lkml <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Tom Vaden <tom.vaden@....com>,
Paolo Bonzini <pbonzini@...hat.com>,
Juergen Gross <jgross@...e.com>,
Alok Kataria <akataria@...are.com>
Subject: Re: [RFC] perf/x86/intel: Disable check_msr for real hw
On Mon, Jun 24, 2019 at 09:46:17AM -0700, Andi Kleen wrote:
> > > The other hypervisors are relatively obscure, but eventually
> > > someone will hit problems.
> >
> > any idea if there's any other flag/way we could use to detect those?
>
> I'm not aware of a generic way to detect any hypervisor unfortunately.
>
> There are hypervisor reserved cpuid ranges, in theory you could
> probe the existence of those. But there might be always some which
> don't have extra CPUIDs.
>
> >
> > adding few virtualization folks to the loop
> > and attaching the original patch
> >
> > thanks,
> > jirka
> >
> >
> > ---
> > Tom Vaden reported false failure of check_msr function, because
> > some servers can do POST tracing and enable LBR tracing during
> > the boot.
>
> Just to understand the original problem, the LBR registers
> get locked somehow? It would be reasonable to not use LBRs
> in this case. We just need to make sure everything
> else is still probed.
Tom, plz correctme if I'm wrongm but AFAIK because the LBR tracing is
enabled during the boot the lbr_from/lbr_to registers will fail the
check_msr 'val_new != val_tmp' check
if there's no good way to detect this, maybe we add boot option
to disable the check_msr check
jirka
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