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Message-Id: <cover.1561346998.git.saiprakash.ranjan@codeaurora.org>
Date: Mon, 24 Jun 2019 09:06:08 +0530
From: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To: Mathieu Poirier <mathieu.poirier@...aro.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
Leo Yan <leo.yan@...aro.org>, Rob Herring <robh+dt@...nel.org>,
devicetree@...r.kernel.org,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Mark Rutland <mark.rutland@....com>
Cc: Rajendra Nayak <rnayak@...eaurora.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
Sibi Sankar <sibis@...eaurora.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Subject: [PATCHv3 0/1] coresight: Do not default to CPU0 for missing CPU phandle
In case of missing CPU phandle, the affinity is set default to
CPU0 which is not a correct assumption. Fix this in coresight
platform to set affinity to invalid and abort the probe in drivers.
Also update the dt-bindings accordingly.
v3:
* Addressed review comments from Suzuki and updated
acpi_coresight_get_cpu.
* Removed patch 2 which had invalid check for online
cpus.
v2:
* Addressed review comments from Suzuki and Mathieu.
* Allows the probe of etm and cpu-debug to abort earlier
in case of unavailability of respective cpus.
Sai Prakash Ranjan (1):
coresight: Do not default to CPU0 for missing CPU phandle
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt | 8 +++++---
.../hwtracing/coresight/coresight-cpu-debug.c | 3 +++
drivers/hwtracing/coresight/coresight-etm3x.c | 3 +++
drivers/hwtracing/coresight/coresight-etm4x.c | 3 +++
drivers/hwtracing/coresight/coresight-platform.c | 16 ++++++++--------
6 files changed, 24 insertions(+), 13 deletions(-)
--
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